Struct rsim::processor::isa_mods::vector::Rvv

pub struct Rvv<uXLEN: PossibleXlen, TElem> {
    vreg: Box<dyn VectorRegisterFile<TElem>>,
    vtype: VType,
    vl: u32,
    vstart: u32,
    _phantom_xlen: PhantomData<uXLEN>,
}

The Vector Unit for the processor. Stores all vector state, including registers. This requires a VecMemInterface<uXLEN, TElem> and VecRegInterface to access other resources.

Fields

vreg: Box<dyn VectorRegisterFile<TElem>>

vtype: VType

vl: u32

vstart: u32

This is used by the hardware to support resuming vector instructions after traps. e.g. if a vector load hits a page fault at element #N, set vstart to N before taking the trap, and the load will resume from vstart when you get back. Reset to zero after every vector load instruction.

This potentially impacts fast paths, e.g. if a fast-path load pulls full lines from memory into a vector register, vstart must be 0.

_phantom_xlen: PhantomData<uXLEN>

Implementations

impl<uXLEN: PossibleXlen, TElem> Rvv<uXLEN, TElem>

pub fn new(vreg: Box<dyn VectorRegisterFile<TElem>>) -> Self

Returns an initialized vector unit.

pub fn reset(&mut self)

Reset the vector unit’s state

fn exec_config(
    &mut self,
    inst_kind: ConfigKind,
    inst: InstructionBits,
    sreg: &mut dyn VecRegInterface<uXLEN>
) -> Result<()>

(Internal) Execute a configuration instruction, e.g. vsetvli family Requires a VecRegInterface.

Arguments

• inst_kind - Which kind of configuration instruction to execute
• inst - Decoded instruction bits
• conn - Connection to external resources

fn get_active_segment_range(&mut self, vm: bool, evl: u32) -> Option<Range<u32>>

Find the last segment index that isn’t masked out. Used to find a tight range of the segments/elements that will actually be processed.

fn fast_check_load_store(
    &mut self,
    addr_provenance: (u64, Provenance),
    rs2: u8,
    vm: bool,
    op: DecodedMemOp,
    sreg: &mut dyn VecRegInterface<uXLEN>
) -> (Result<bool>, Range<u64>)

Try doing fast-path capability checks for accesses for a vector load/store. Fast-paths exist for all accesses, although in hardware some may not be as fast as others. Return values:

• Ok(true) if the fast-path check raised no capability exceptions
  • Therefore the full access should not raise any capability exceptions
• Ok(false) if the fast-path check failed in a tolerable manner
  • Therefore the full access may raise a capability exception
  • A tolerable fast-path failure = fault-only-first, which might absorb the exception.
• Err() if the fast-path check failed in a not-tolerable manner panics if all elements are masked out

fn get_load_store_accesses(
    &mut self,
    rd: u8,
    addr_p: (u64, Provenance),
    rs2: u8,
    vm: bool,
    op: DecodedMemOp
) -> Result<Vec<(VectorElem, u64)>>

Converts a decoded memory operation to the list of accesses it performs.

fn exec_load_store(
    &mut self,
    expected_addr_range: Range<u64>,
    rd: u8,
    rs1: u8,
    rs2: u8,
    vm: bool,
    op: DecodedMemOp,
    sreg: &mut dyn VecRegInterface<uXLEN>,
    mem: &mut dyn VecMemInterface<uXLEN, TElem>
) -> Result<()>

Execute a decoded memory access, assuming all access checks have already been performed.

fn load_to_vreg(
    &mut self,
    mem: &mut dyn VecMemInterface<uXLEN, TElem>,
    eew: Sew,
    addr_provenance: (u64, Provenance),
    vd_base: u8,
    idx_from_base: u32
) -> Result<()>

Load a value of width eew from a given address addr into a specific element idx_from_base of a vector register group starting at vd_base

fn store_to_mem(
    &mut self,
    mem: &mut dyn VecMemInterface<uXLEN, TElem>,
    eew: Sew,
    addr_provenance: (u64, Provenance),
    vd_base: u8,
    idx_from_base: u32
) -> Result<()>

Stores a value of width eew from a specific element idx_from_base of a vector register group starting at vd_base into a given address addr

pub fn dump(&self)

Dump vector unit state to standard output.

Trait Implementations

impl<uXLEN: PossibleXlen, TElem> CSRProvider<uXLEN> for Rvv<uXLEN, TElem>

fn has_csr(&self, csr: u32) -> bool

Does the Provider provide access to a given CSR?

fn csr_atomic_read_write(
    &mut self,
    csr: u32,
    _need_read: bool,
    _write_val: uXLEN
) -> Result<Option<uXLEN>>

Atomic Read/Write a CSR

fn csr_atomic_read_set(
    &mut self,
    csr: u32,
    set_bits: Option<uXLEN>
) -> Result<uXLEN>

Atomically read and set specific bits in a CSR

fn csr_atomic_read_clear(
    &mut self,
    _csr: u32,
    _clear_bits: Option<uXLEN>
) -> Result<uXLEN>

Atomically read and clear specific bits in a CSR

impl<uXLEN: PossibleXlen, TElem> IsaMod<(&'_ mut (dyn VecRegInterface<uXLEN> + '_), &'_ mut (dyn VecMemInterface<uXLEN, TElem> + '_))> for Rvv<uXLEN, TElem>

type Pc = ()

fn will_handle(&self, opcode: Opcode, inst: InstructionBits) -> bool

Return true if this ISA module should handle the given instruction

fn execute(
    &mut self,
    opcode: Opcode,
    inst: InstructionBits,
    inst_bits: u32,
    conn: VecInterface<'_, uXLEN, TElem>
) -> ProcessorResult<Option<()>>

Execute a vector-specific instruction, e.g. vector arithmetic, loads, configuration Requires a VecRegInterface and a VecMemInterface.

Arguments

• opcode - The major opcode of the instruction
• inst - Decoded instruction bits
• inst_bits - Raw instruction bits (TODO - we shouldn’t need this)
• conn - Connection to external resources