Trait rsim::processor::isa_mods::IsaMod[−][src]

pub trait IsaMod<TConn> {
    type Pc;
    fn will_handle(&self, opcode: Opcode, inst: InstructionBits) -> bool;

    fn execute(
        &mut self, 
        opcode: Opcode, 
        inst: InstructionBits, 
        inst_bits: u32, 
        conn: TConn
    ) -> ProcessorResult<Option<Self::Pc>>;
}

Trait for all ISA modules.

Uses a TConn value to connect to processor state: for example, the Rv64im module takes a connection holding a reference to a 64-bit register file, and a reference to main memory.

Associated Types

type Pc[src]

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Required methods

fn will_handle(&self, opcode: Opcode, inst: InstructionBits) -> bool[src]

Return true if this ISA module should handle the given instruction

fn execute(
    &mut self,
    opcode: Opcode,
    inst: InstructionBits,
    inst_bits: u32,
    conn: TConn
) -> ProcessorResult<Option<Self::Pc>>[src]

Execute the given instruction, returning the new PC (or None if continuing as normal)

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Implementors

impl IsaMod<XCheri64Conn<'_>> for Rv64imCapabilityMode[src]

type Pc = u64

impl IsaMod<XCheri64Conn<'_>> for XCheri64[src]

type Pc = Cc128Cap

impl IsaMod<RvimConn<'_, u32>> for Rv32im[src]

type Pc = u32

impl IsaMod<RvimConn<'_, u64>> for Rv64im[src]

type Pc = u64

impl<T> IsaMod<ZicsrConn<'_, T>> for Zicsr<T> where
    T: From<u8>, [src]

type Pc = T

impl<uXLEN: PossibleXlen, TElem> IsaMod<(&'_ mut (dyn VecRegInterface<uXLEN> + '_), &'_ mut (dyn VecMemInterface<uXLEN, TElem> + '_))> for Rvv<uXLEN, TElem>[src]

type Pc = ()

fn execute(
    &mut self,
    opcode: Opcode,
    inst: InstructionBits,
    inst_bits: u32,
    conn: VecInterface<'_, uXLEN, TElem>
) -> ProcessorResult<Option<()>>[src]

Execute a vector-specific instruction, e.g. vector arithmetic, loads, configuration Requires a VecRegInterface and a VecMemInterface.

Arguments

  • opcode - The major opcode of the instruction
  • inst - Decoded instruction bits
  • inst_bits - Raw instruction bits (TODO - we shouldn’t need this)
  • conn - Connection to external resources
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