Trait rsim::processor::isa_mods::csrs::CSRProvider[−][src]

pub trait CSRProvider<T> {
    fn has_csr(&self, csr: u32) -> bool;

    fn csr_atomic_read_write(
        &mut self, 
        csr: u32, 
        need_read: bool, 
        write_val: T
    ) -> ProcessorResult<Option<T>>;

    fn csr_atomic_read_set(
        &mut self, 
        csr: u32, 
        set_bits: Option<T>
    ) -> ProcessorResult<T>;

    fn csr_atomic_read_clear(
        &mut self, 
        csr: u32, 
        clear_bits: Option<T>
    ) -> ProcessorResult<T>;
}

Required methods

fn has_csr(&self, csr: u32) -> bool[src]

Does the Provider provide access to a given CSR?

fn csr_atomic_read_write(
    &mut self,
    csr: u32,
    need_read: bool,
    write_val: T
) -> ProcessorResult<Option<T>>[src]

Atomic Read/Write a CSR

Will only be called on csr if has_csr(csr) == true

Reads can have side-effects, and some variants of the instruction disable that. If `need_read == false’, it won’t perform a read or any side-effects, and will return an Ok(None). Otherwise will return an Ok(Some()) with the previous CSR value, and execute side-effects.

fn csr_atomic_read_set(
    &mut self,
    csr: u32,
    set_bits: Option<T>
) -> ProcessorResult<T>[src]

Atomically read and set specific bits in a CSR

Will only be called on csr if has_csr(csr) == true

If `set_bits == None’, no write will be performed (thus no side-effects of the write will happen). The CSR will always be read, and those side-effects will always be applied.

fn csr_atomic_read_clear(
    &mut self,
    csr: u32,
    clear_bits: Option<T>
) -> ProcessorResult<T>[src]

Atomically read and clear specific bits in a CSR

Will only be called on csr if has_csr(csr) == true

If `clear_bits == None’, no write will be performed (thus no side-effects of the write will happen). The CSR will always be read, and those side-effects will always be applied.

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Implementors

impl CSRProvider<u32> for ProcessorCSRs32[src]

impl CSRProvider<u64> for Rv64imvProcessorCSRs[src]

impl CSRProvider<u64> for Rv64imvXCheriProcessorCSRs[src]

impl<uXLEN: PossibleXlen, TElem> CSRProvider<uXLEN> for Rvv<uXLEN, TElem>[src]

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