Module rsim::processor::isa_mods::vector [−][src]
Modules
| conns | |
| decode | |
| registers | |
| types |
Structs
| CheriVectorRegisterFile | Register file which holds 128-bit integer vectors OR one tagged capability per vector. |
| IntVectorRegisterFile | Register file which holds 128-bit integer vectors. |
| Rvv | The Vector Unit for the processor.
Stores all vector state, including registers.
This requires a VecMemInterface<uXLEN, TElem> and VecRegInterface |
| VType | Vector type information |
| VectorElem | A struct describing an element of a vector register group |
Enums
| ConfigKind | Config instruction kind enum |
| DecodedMemOp | The different kinds of RISC-V V vector loads/stores. One top-level enum which encapsulates Strided access (also used for basic unit-stride access), Indexed access, and the special cases of unit-stride access (e.g. whole-register, bytemasked, fault-only-first). |
| Lmul | Length-Mul enum |
| MemOpDir | The “direction” of a memory operation. Used by DecodedMemOp. |
| Sew | Selected-Element-Width enum |
| UnitStrideLoadOp | Special variants of vector loads with unit-stride |
| UnitStrideStoreOp | Special variants of vector stores with unit-stride |
Constants
| VLEN | Vector register length in bits |
Traits
| VecMemInterface | Common trait for interfaces to memory |
| VecRegInterface | |
| VectorRegisterFile | Trait for a vector register file where VLEN=128, ELEN=128. Data is stored in TElem, which can be plain integers or a SafeTaggedCap (which implicitly adds 1-bit) |
Functions
| extract_bits | Complementary function to replace_bits |
| replace_bits | Function that replaces the bits of a value in a specific range with the bits at the bottom of a new value.
The Range is expected in Verilog-style, i.e. all-inclusive unlike typical usages of Range.
Panics if new_data has 1s outside of the range specified by |
| val_times_lmul_over_sew | Function that evaluates (X * LMUL) / SEW from their enum values |
Type Definitions
| Provenance | Struct indicating the providence of a pointer. |
| Rv32v | RISC-V Vector unit for RV32 ISAs |
| Rv64Cheriv | RISC-V Vector unit for RV64 + CHERI ISAs |
| Rv64v | RISC-V Vector unit for RV64 non-CHERI ISAs |
| VecInterface | Helper type combining VecRegInterface and VecMemInterface |
| uVLEN | Unsigned type of length VLEN |