Trait rsim::processor::isa_mods::vector::registers::VectorRegisterFile[−][src]

pub trait VectorRegisterFile<TElem> {
    fn load_vreg_elem(
        &self, 
        eew: Sew, 
        vd_base: u8, 
        idx_from_base: u32
    ) -> Result<TElem>;

    fn load_vreg_elem_int(
        &self, 
        eew: Sew, 
        vd_base: u8, 
        idx_from_base: u32
    ) -> Result<u128>;

    fn store_vreg_elem(
        &mut self, 
        eew: Sew, 
        vd_base: u8, 
        idx_from_base: u32, 
        val: TElem
    ) -> Result<()>;

    fn store_vreg_elem_int(
        &mut self, 
        eew: Sew, 
        vd_base: u8, 
        idx_from_base: u32, 
        val: u128
    ) -> Result<()>;

    fn load_vreg(&mut self, vs: u8) -> Result<TElem>;

    fn load_vreg_int(&mut self, vs: u8) -> Result<u128>;

    fn store_vreg(&mut self, vs: u8, val: TElem) -> Result<()>;

    fn store_vreg_int(&mut self, vs: u8, val: u128) -> Result<()>;

    fn seg_masked_out(&self, vm: bool, i: u32) -> bool;

    fn dump(&self);

    fn reset(&mut self);
}

Trait for a vector register file where VLEN=128, ELEN=128. Data is stored in TElem, which can be plain integers or a SafeTaggedCap (which implicitly adds 1-bit)

Required methods

fn load_vreg_elem(
    &self,
    eew: Sew,
    vd_base: u8,
    idx_from_base: u32
) -> Result<TElem>[src]

Load a value from an element in a vertex register group, with specified EEW Requires the type of the value to store matches the EEW.

Example: if EEW=32bits, VLEN=128bits (4 32-bit elements per register), vd = 3, idx = 5, the actual vd = 3 + (idx_from_base / 4) = 4, and the actual idx = idx_from_base % 4 = 1. this would return v4[64:32] (element 1 of v4)

fn load_vreg_elem_int(
    &self,
    eew: Sew,
    vd_base: u8,
    idx_from_base: u32
) -> Result<u128>[src]

fn store_vreg_elem(
    &mut self,
    eew: Sew,
    vd_base: u8,
    idx_from_base: u32,
    val: TElem
) -> Result<()>[src]

Store a value in an element in a vertex register group, with specified EEW. Requires the type of the value to store matches the EEW.

Example: if EEW=32bits, VLEN=128bits (4 32-bit elements per register), vd_base = 3, idx_from_base = 5, the actual vd = 3 + (idx_from_base / 4) = 4, and the actual idx = idx_from_base % 4 = 1. This would store val into v4[64:32] (element 1 of v4)

fn store_vreg_elem_int(
    &mut self,
    eew: Sew,
    vd_base: u8,
    idx_from_base: u32,
    val: u128
) -> Result<()>[src]

fn load_vreg(&mut self, vs: u8) -> Result<TElem>[src]

fn load_vreg_int(&mut self, vs: u8) -> Result<u128>[src]

fn store_vreg(&mut self, vs: u8, val: TElem) -> Result<()>[src]

fn store_vreg_int(&mut self, vs: u8, val: u128) -> Result<()>[src]

fn seg_masked_out(&self, vm: bool, i: u32) -> bool[src]

Returns true if the mask is enabled and element i has been masked out, e.g. that it should not be touched.

fn dump(&self)[src]

fn reset(&mut self)[src]

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Implementors

impl VectorRegisterFile<SafeTaggedCap> for CheriVectorRegisterFile[src]

impl VectorRegisterFile<u128> for IntVectorRegisterFile[src]

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