Crate rsim[−][src]
Library for emulating various RISC-V processors. Supports 32 or 64-bit ISAs, “i”, “m”, “Zcsr”, “v”, “xcheri” extensions.
If you’re coming from my MPhil project, you probably want to see the vector documentation
Re-exports
pub use processor::models; | |
pub use processor::isa_mods; |
Modules
| memory | Publically exposed memory-related structures. Includes capability and integer-addressed memory. |
| processor | Main module with all processor elements, ISA modules, and models. |
Enums
| Cc128 | Publically exposed CHERI-related structures. All pulled from [rust_cheri_compressed_cap]. |
Traits
| CheriRVFuncs | Publically exposed CHERI-related structures. All pulled from [rust_cheri_compressed_cap]. |
| CompressedCapability | Publically exposed CHERI-related structures. All pulled from [rust_cheri_compressed_cap]. |
Type Definitions
| Cc128Cap | Publically exposed CHERI-related structures. All pulled from [rust_cheri_compressed_cap]. |