Struct rsim::processor::isa_mods::RvimConn [−][src]
pub struct RvimConn<'a, uXLEN: PossibleXlen> { pub pc: uXLEN, pub sreg: &'a mut dyn RegisterFile<uXLEN>, pub memory: &'a mut dyn Memory, }
Connection to a RISC-V I+M ISA module.
Fields
pc: uXLENsreg: &'a mut dyn RegisterFile<uXLEN>memory: &'a mut dyn MemoryTrait Implementations
impl IsaMod<RvimConn<'_, u32>> for Rv32im[src]
impl IsaMod<RvimConn<'_, u32>> for Rv32im[src]type Pc = u32
fn will_handle(&self, opcode: Opcode, _inst: InstructionBits) -> bool[src]
fn execute(
&mut self,
opcode: Opcode,
inst: InstructionBits,
_inst_bits: u32,
conn: Rv32imConn<'_>
) -> ProcessorResult<Option<Self::Pc>>[src]
&mut self,
opcode: Opcode,
inst: InstructionBits,
_inst_bits: u32,
conn: Rv32imConn<'_>
) -> ProcessorResult<Option<Self::Pc>>
impl IsaMod<RvimConn<'_, u64>> for Rv64im[src]
impl IsaMod<RvimConn<'_, u64>> for Rv64im[src]type Pc = u64
fn will_handle(&self, opcode: Opcode, _inst: InstructionBits) -> bool[src]
fn execute(
&mut self,
opcode: Opcode,
inst: InstructionBits,
_inst_bits: u32,
conn: Rv64imConn<'_>
) -> ProcessorResult<Option<Self::Pc>>[src]
&mut self,
opcode: Opcode,
inst: InstructionBits,
_inst_bits: u32,
conn: Rv64imConn<'_>
) -> ProcessorResult<Option<Self::Pc>>
Auto Trait Implementations
impl<'a, uXLEN> !RefUnwindSafe for RvimConn<'a, uXLEN>
impl<'a, uXLEN> !Send for RvimConn<'a, uXLEN>
impl<'a, uXLEN> !Sync for RvimConn<'a, uXLEN>
impl<'a, uXLEN> Unpin for RvimConn<'a, uXLEN> where
uXLEN: Unpin,
uXLEN: Unpin,