Trait rsim::processor::isa_mods::vector::VecRegInterface[−][src]

pub trait VecRegInterface<uXLEN: PossibleXlen> {
    fn sreg_read_xlen(&mut self, reg: u8) -> Result<uXLEN>;

    fn sreg_write_xlen(&mut self, reg: u8, val: uXLEN) -> Result<()>;

    fn get_addr_provenance(&mut self, reg: u8) -> Result<(u64, Provenance)>;

    fn check_addr_range_against_provenance(
        &mut self, 
        addr_range: Range<u64>, 
        prov: Provenance, 
        dir: MemOpDir
    ) -> Result<()>;

    fn check_elem_bounds_against_provenance(
        &mut self, 
        eew: Sew, 
        addr_provenance: (u64, Provenance), 
        dir: MemOpDir
    ) -> Result<()>;
}

Required methods

fn sreg_read_xlen(&mut self, reg: u8) -> Result<uXLEN>[src]

Read a value XLEN from a register, not an address

fn sreg_write_xlen(&mut self, reg: u8, val: uXLEN) -> Result<()>[src]

Write a value XLEN to a register, not an address

fn get_addr_provenance(&mut self, reg: u8) -> Result<(u64, Provenance)>[src]

Get a raw address value + the provenance of that address from a register. The address can be changed, and then VecMemInterface::load_from_memory and VecMemInterface::store_to_memory can reuse the providence with the modified address

fn check_addr_range_against_provenance(
    &mut self,
    addr_range: Range<u64>,
    prov: Provenance,
    dir: MemOpDir
) -> Result<()>[src]

Check if the provenance p allows accesses to the specified address range in the specified direction (load or store). Note: This addr_range is at the 1-byte level - if you want to access a range of u64s, make sure the range includes the end of the last u64

fn check_elem_bounds_against_provenance(
    &mut self,
    eew: Sew,
    addr_provenance: (u64, Provenance),
    dir: MemOpDir
) -> Result<()>[src]

As for check_addr_range_against_provenance, but for a single element of given width

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Implementors

impl<'a> VecRegInterface<u64> for CheriRV64RegisterFile[src]

impl<'a> VecRegInterface<u64> for IntegerModeCheriRV64RegisterFile<'a>[src]

impl<'a, uXLEN: PossibleXlen> VecRegInterface<uXLEN> for RvRegisterFile<uXLEN>[src]

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