Enum rsim::processor::isa_mods::vector::Lmul

pub enum Lmul {
    eEighth,
    eQuarter,
    eHalf,
    e1,
    e2,
    e4,
    e8,
}

Length-Mul enum

RISC-V V allows programs to group vector registers together for greater theoretical parallelism. For example, configuring LMUL=8 means that subsequent vector instructions will operate on 8 vector registers worth of elements.

This requires care if you are resizing elements. An example program in v1.0 of the specification (section 6.4, p28) sets LMUL=4, vtype=16-bit for initial operations. This will operate on LMUL * VLEN / SEW = 4 * VLEN / 16 = VLEN/4 elements.

It then widens the elements to 32-bit using a widening vector multiply. To ensure the following instructions operate on the same number of elements, they reconfigure with doubled LMUL. LMUL = 8, vtype = 32-bit => LMUL * VLEN / SEW = 8 * VLEN / 32 = VLEN/4 elements, same as before.

Variants

eEighth

eQuarter

eHalf

e1

e2

e4

e8

Implementations

impl Lmul

pub fn num_registers_consumed(&self) -> u8

Returns the number of vector registers a group actually consumes with this Lmul.

Trait Implementations

impl Clone for Lmul

fn clone(&self) -> Lmul

Returns a copy of the value.

pub fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Lmul

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq<Lmul> for Lmul

fn eq(&self, other: &Lmul) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]

pub fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl Copy for Lmul

impl Eq for Lmul

impl StructuralEq for Lmul

impl StructuralPartialEq for Lmul