Struct rsim::processor::isa_mods::vector::registers::CheriVectorRegisterFile

pub struct CheriVectorRegisterFile {
    vreg: [SafeTaggedCap; 32],
}

Register file which holds 128-bit integer vectors OR one tagged capability per vector.

Fields

vreg: [SafeTaggedCap; 32]

Trait Implementations

impl Default for CheriVectorRegisterFile

fn default() -> Self

Returns the “default value” for a type.

impl VectorRegisterFile<SafeTaggedCap> for CheriVectorRegisterFile

fn load_vreg(&mut self, vs: u8) -> Result<SafeTaggedCap>

fn load_vreg_int(&mut self, vs: u8) -> Result<u128>

fn store_vreg(&mut self, vd: u8, val: SafeTaggedCap) -> Result<()>

fn store_vreg_int(&mut self, vd: u8, val: u128) -> Result<()>

fn load_vreg_elem(
    &self,
    eew: Sew,
    vd_base: u8,
    idx_from_base: u32
) -> Result<SafeTaggedCap>

Load a value from an element in a vertex register group, with specified EEW Requires the type of the value to store matches the EEW.

fn load_vreg_elem_int(
    &self,
    eew: Sew,
    vd_base: u8,
    idx_from_base: u32
) -> Result<u128>

fn store_vreg_elem(
    &mut self,
    eew: Sew,
    vd_base: u8,
    idx_from_base: u32,
    val: SafeTaggedCap
) -> Result<()>

Store a value in an element in a vertex register group, with specified EEW. Requires the type of the value to store matches the EEW.

fn store_vreg_elem_int(
    &mut self,
    eew: Sew,
    vd_base: u8,
    idx_from_base: u32,
    val: u128
) -> Result<()>

fn seg_masked_out(&self, vm: bool, i: u32) -> bool

Returns true if the mask is enabled and element i has been masked out, e.g. that it should not be touched.

fn dump(&self)

fn reset(&mut self)