Module rsim::processor::isa_mods::vector::registers [−][src]
Structs
| CheriVectorRegisterFile | Register file which holds 128-bit integer vectors OR one tagged capability per vector. |
| IntVectorRegisterFile | Register file which holds 128-bit integer vectors. |
Traits
| VectorRegisterFile | Trait for a vector register file where VLEN=128, ELEN=128. Data is stored in TElem, which can be plain integers or a SafeTaggedCap (which implicitly adds 1-bit) |
Functions
| bit_range_for_element | Returns (register idx, bit range) for an element of a given width |
| extract_bits | Complementary function to replace_bits |
| replace_bits | Function that replaces the bits of a value in a specific range with the bits at the bottom of a new value.
The Range is expected in Verilog-style, i.e. all-inclusive unlike typical usages of Range.
Panics if new_data has 1s outside of the range specified by |