Struct rsim::processor::elements::cheri::IntegerModeCheriAggregateMemory

pub struct IntegerModeCheriAggregateMemory<'a> {
    base_mem: &'a mut CheriAggregateMemory,
    base_cap: Cc128Cap,
}

Wrapper for a reference to CheriAggregateMemory that allows integer-mode accesses. Exposes MemoryOf<{u8,u16,u32,u64}, TAddr=u64>.

Fields

base_mem: &'a mut CheriAggregateMemory

base_cap: Cc128Cap

Implementations

impl<'a> IntegerModeCheriAggregateMemory<'a>

pub fn wrap(base_mem: &'a mut CheriAggregateMemory, base_cap: Cc128Cap) -> Self

Trait Implementations

impl<'a> CheriMemory<u64> for IntegerModeCheriAggregateMemory<'a>

Combine MemoryOf<u8,u16,u32,u64> with MemoryOf

fn load_maybe_cap(&mut self, addr: TAddr) -> MemoryResult<SafeTaggedCap>

fn store_maybe_cap(
    &mut self,
    addr: TAddr,
    val: SafeTaggedCap
) -> MemoryResult<()>

fn store_cap(&mut self, addr: TAddr, val: Cc128Cap) -> MemoryResult<()>

impl<'a> Memory<u64> for IntegerModeCheriAggregateMemory<'a>

fn range(&self) -> Range<usize>

The mapped address range for this Memory. All addresses passed to read,write must be within this range. Guaranteed to be at least 4 bytes in size, both ends will be 4-byte aligned.

fn as_any(&self) -> &dyn Any

fn load_u8(&mut self, addr: TAddr) -> MemoryResult<u8>

fn load_u16(&mut self, addr: TAddr) -> MemoryResult<u16>

fn load_u32(&mut self, addr: TAddr) -> MemoryResult<u32>

fn load_u64(&mut self, addr: TAddr) -> MemoryResult<u64>

fn store_u8(&mut self, addr: TAddr, val: u8) -> MemoryResult<()>

fn store_u16(&mut self, addr: TAddr, val: u16) -> MemoryResult<()>

fn store_u32(&mut self, addr: TAddr, val: u32) -> MemoryResult<()>

fn store_u64(&mut self, addr: TAddr, val: u64) -> MemoryResult<()>

impl<'a, TData> MemoryOf<TData, u64> for IntegerModeCheriAggregateMemory<'a> where
    CheriAggregateMemory: MemoryOf<TData, Cc128Cap>, 

Reimplement basic MemoryOf<TData, TAddr=u64> for the integer mode memory. Integer addresses are passed to the underlying CheriAggregateMemory inside the base capability, and all checking/security is done inside the CheriAggregateMemory.

fn read(&mut self, addr: u64) -> MemoryResult<TData>

fn write(&mut self, addr: u64, val: TData) -> MemoryResult<()>

impl<'a> VecMemInterface<u64, SafeTaggedCap> for IntegerModeCheriAggregateMemory<'a>

fn load_from_memory(
    &mut self,
    eew: Sew,
    addr_provenance: (u64, Provenance)
) -> Result<SafeTaggedCap>

Use an address, provenance pair to read a vector element from memory

fn store_to_memory(
    &mut self,
    eew: Sew,
    val: SafeTaggedCap,
    addr_provenance: (u64, Provenance)
) -> Result<()>

Use an address, provenance pair to write a vector element to memory