Trait rsim::processor::elements::memory::MemoryOf[−][src]

pub trait MemoryOf<TData, TAddr = u64> where
    TData: Sized, {
    fn read(&mut self, addr: TAddr) -> MemoryResult<TData>;

    fn write(&mut self, addr: TAddr, val: TData) -> MemoryResult<()>;
}

Internal trait defining functions for reading/writing values of type TData from a memory, using values of type TAddr as addresses (TAddr is usually u64 for non-CHERI memory.)

Required methods

fn read(&mut self, addr: TAddr) -> MemoryResult<TData>[src]

fn write(&mut self, addr: TAddr, val: TData) -> MemoryResult<()>[src]

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Implementors

impl MemoryOf<SafeTaggedCap, CcxCap<Cc128>> for CheriAggregateMemory[src]

Impl a capability-aware view of memory for CHERI instructions e.g. a CHERI Load instruction, which is allowed to load capabilities, would use this version.

impl MemoryOf<bool, u64> for TagMemory[src]

impl MemoryOf<u8, u64> for MemoryBacking[src]

impl MemoryOf<u16, u64> for MemoryBacking[src]

impl MemoryOf<u32, u64> for MemoryBacking[src]

impl MemoryOf<u64, u64> for MemoryBacking[src]

impl<'a, TData> MemoryOf<TData, u64> for IntegerModeCheriAggregateMemory<'a> where
    CheriAggregateMemory: MemoryOf<TData, Cc128Cap>, [src]

Reimplement basic MemoryOf<TData, TAddr=u64> for the integer mode memory. Integer addresses are passed to the underlying CheriAggregateMemory inside the base capability, and all checking/security is done inside the CheriAggregateMemory.

impl<TData> MemoryOf<TData, u64> for AggregateMemory where
    dyn Memory: MemoryOf<TData>, [src]

Foreach TData, where Memory implements MemoryOf, re-implement it for AggregateMemory TData = u8,u16,u32,u64

impl<TData> MemoryOf<TData, u64> for IOMemory where
    TData: Into<u64> + Default,
    dyn Memory: MemoryOf<TData>, [src]

impl<TData> MemoryOf<TData, CcxCap<Cc128>> for CheriAggregateMemory where
    AggregateMemory: MemoryOf<TData, u64>, [src]

Implement MemoryOf addressed by Cc128Cap, which does all necessary validity checks, for every TData in {u8,u16,u32,u64}

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