Module rsim::processor::elements::cheri[−][src]

Modules

CheriAggregateMemory	Wrapper for AggregateMemory64 that keeps tags, supports MemoryOf for reading/writing capabilities. All other Memory variants clear associated tag bits on write.
CheriRV64RegisterFile	Register file for 64-bit RISC-V that can hold tagged 128-bit capabilities.
IntegerModeCheriAggregateMemory	Wrapper for a reference to CheriAggregateMemory that allows integer-mode accesses. Exposes MemoryOf<{u8,u16,u32,u64}, TAddr=u64>.
IntegerModeCheriRV64RegisterFile
TagMemory	Memory holding tags for capabilities. Implements MemoryOf, which checks if the supplied address is a multiple of 16-bytes i.e. the size of a capability.

Cc128	Defines the CC128 capability profile as an implementation of the CompressedCapability trait.
SafeTaggedCap	Enumeration that stores either raw data or a valid capability. The capability inside ValidCap(Cc128Cap) will always have its tag bit = True as long as SafeTaggedCap::ValidCap is not created manually.

CheriMemory
CheriRVFuncs	Trait exposing the utility functions used to specify CHERI-RISC-V behaviour in Tech Report 951. Behaviour is derived from the Sail specification
CompressedCapability	Trait defining an Rust version of the public API for a specific capability type. A type X implementing CompressedCapability is equivalent to the API provided by `cheri_compressed_cap_X.h` in C, where `ccx_cap_t` is equivalent to [CcxCap].

cap_bounds_range	Return the range of addresses you can access with a capability
check_bounds_against_capability	Checks that a capability allows access to a given range of byte addresses
check_capability	Checks that a capability allows access to a `TData`-sized object at the current cursor
check_obj_bounds_against_capability	Checks that a capability allows access to a `TData`-sized object at the given `addr`