Struct rsim::processor::models::rv64imvxcheri::Rv64imvXCheriProcessor[][src]

pub struct Rv64imvXCheriProcessor {
    pub running: bool,
    pub memory: CheriAggregateMemory,
    start_pc: u64,
    pcc: Cc128Cap,
    ddc: Cc128Cap,
    max_cap: Cc128Cap,
    sreg: CheriRV64RegisterFile,
    csrs: Rv64imvXCheriProcessorCSRs,
    initial_mode: CheriExecMode,
}

RISC-V Processor Model where XLEN=64-bit, with CHERI support. Can execute in Integer or Capability mode. Holds scalar registers and configuration, all other configuration stored in Rv64imvXCheriProcessorModules

Fields

running: boolmemory: CheriAggregateMemorystart_pc: u64pcc: Cc128Capddc: Cc128Capmax_cap: Cc128Capsreg: CheriRV64RegisterFilecsrs: Rv64imvXCheriProcessorCSRsinitial_mode: CheriExecMode

Implementations

impl Rv64imvXCheriProcessor[src]

pub fn new(
    start_pc: u64,
    mem: CheriAggregateMemory,
    mode: CheriExecMode
) -> (Rv64imvXCheriProcessor, Rv64imvXCheriProcessorModules)
[src]

Create a new processor and vector unit which operates on given memory.

Arguments

  • mem - The memory the processor should hold. Currently a value, not a reference.

fn zicsr_conn<'a, 'b>(&'a mut self, rvv: &'a mut Rv64Cheriv) -> Zicsr64Conn<'b> where
    'a: 'b, 
[src]

fn xcheri64_conn<'a, 'b>(&'a mut self, mode: CheriExecMode) -> XCheri64Conn<'b> where
    'a: 'b, 
[src]

fn process_inst(
    &mut self,
    mods: &mut Rv64imvXCheriProcessorModules,
    inst_bits: u32,
    opcode: Opcode,
    inst: InstructionBits
) -> Result<Cc128Cap>
[src]

Process an instruction, returning the new PC value or any execution error

Arguments

  • v_unit - The associated vector unit, which will execute vector instructions if they are found.
  • inst_bits - The raw instruction bits
  • opcode - The major opcode of the decoded instruction
  • inst - The fields of the decoded instruction

Trait Implementations

impl Processor<Rv64imvXCheriProcessorModules> for Rv64imvXCheriProcessor[src]

fn reset(&mut self, _mods: &mut Rv64imvXCheriProcessorModules)[src]

Reset the processor and associated vector unit

fn exec_step(&mut self, mods: &mut Rv64imvXCheriProcessorModules) -> Result<()>[src]

Run a fetch-decode-execute step on the processor, executing a single instruction

Arguments

  • v_unit - The associated vector unit, which will execute vector instructions if they are found.

fn dump(&self, mods: &Rv64imvXCheriProcessorModules)[src]

Dump processor and vector unit state to standard output.

Auto Trait Implementations

impl !RefUnwindSafe for Rv64imvXCheriProcessor

impl !Send for Rv64imvXCheriProcessor

impl !Sync for Rv64imvXCheriProcessor

impl Unpin for Rv64imvXCheriProcessor

impl !UnwindSafe for Rv64imvXCheriProcessor

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.