Struct rsim::processor::isa_mods::XCheri64Conn [−][src]
pub struct XCheri64Conn<'a> { pub pcc: Cc128Cap, pub sreg: &'a mut CheriRV64RegisterFile, pub memory: &'a mut CheriAggregateMemory, pub mode: CheriExecMode, pub ddc: Cc128Cap, }
Connection to register state for 64-bit CHERI-aware ISA modules. Used by XCheri64 and Rv64imCapabilityMode.
Fields
pcc: Cc128Cap
sreg: &'a mut CheriRV64RegisterFile
memory: &'a mut CheriAggregateMemory
mode: CheriExecMode
ddc: Cc128Cap
Trait Implementations
impl IsaMod<XCheri64Conn<'_>> for XCheri64
[src]
impl IsaMod<XCheri64Conn<'_>> for XCheri64
[src]type Pc = Cc128Cap
fn will_handle(&self, opcode: Opcode, inst: InstructionBits) -> bool
[src]
fn execute(
&mut self,
opcode: Opcode,
inst: InstructionBits,
_inst_bits: u32,
conn: XCheri64Conn<'_>
) -> ProcessorResult<Option<Self::Pc>>
[src]
&mut self,
opcode: Opcode,
inst: InstructionBits,
_inst_bits: u32,
conn: XCheri64Conn<'_>
) -> ProcessorResult<Option<Self::Pc>>
impl IsaMod<XCheri64Conn<'_>> for Rv64imCapabilityMode
[src]
impl IsaMod<XCheri64Conn<'_>> for Rv64imCapabilityMode
[src]type Pc = u64
fn will_handle(&self, opcode: Opcode, _inst: InstructionBits) -> bool
[src]
fn execute(
&mut self,
opcode: Opcode,
inst: InstructionBits,
_inst_bits: u32,
conn: XCheri64Conn<'_>
) -> ProcessorResult<Option<Self::Pc>>
[src]
&mut self,
opcode: Opcode,
inst: InstructionBits,
_inst_bits: u32,
conn: XCheri64Conn<'_>
) -> ProcessorResult<Option<Self::Pc>>