Struct rsim::processor::isa_mods::CheriVectorRegisterFile [−][src]
pub struct CheriVectorRegisterFile { vreg: [SafeTaggedCap; 32], }
Register file which holds 128-bit integer vectors OR one tagged capability per vector.
Fields
vreg: [SafeTaggedCap; 32]
Trait Implementations
impl Default for CheriVectorRegisterFile
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impl Default for CheriVectorRegisterFile
[src]impl VectorRegisterFile<SafeTaggedCap> for CheriVectorRegisterFile
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impl VectorRegisterFile<SafeTaggedCap> for CheriVectorRegisterFile
[src]fn load_vreg(&mut self, vs: u8) -> Result<SafeTaggedCap>
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fn load_vreg_int(&mut self, vs: u8) -> Result<u128>
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fn store_vreg(&mut self, vd: u8, val: SafeTaggedCap) -> Result<()>
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fn store_vreg_int(&mut self, vd: u8, val: u128) -> Result<()>
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fn load_vreg_elem(
&self,
eew: Sew,
vd_base: u8,
idx_from_base: u32
) -> Result<SafeTaggedCap>
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&self,
eew: Sew,
vd_base: u8,
idx_from_base: u32
) -> Result<SafeTaggedCap>
fn load_vreg_elem_int(
&self,
eew: Sew,
vd_base: u8,
idx_from_base: u32
) -> Result<u128>
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&self,
eew: Sew,
vd_base: u8,
idx_from_base: u32
) -> Result<u128>
fn store_vreg_elem(
&mut self,
eew: Sew,
vd_base: u8,
idx_from_base: u32,
val: SafeTaggedCap
) -> Result<()>
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&mut self,
eew: Sew,
vd_base: u8,
idx_from_base: u32,
val: SafeTaggedCap
) -> Result<()>
fn store_vreg_elem_int(
&mut self,
eew: Sew,
vd_base: u8,
idx_from_base: u32,
val: u128
) -> Result<()>
[src]
&mut self,
eew: Sew,
vd_base: u8,
idx_from_base: u32,
val: u128
) -> Result<()>