Struct rsim::processor::models::Processor32

pub struct Processor32 {
    pub running: bool,
    pub memory: AggregateMemory,
    pc: u32,
    sreg: RvRegisterFile<u32>,
    csrs: ProcessorCSRs32,
}

RISC-V Processor Model where XLEN=32-bit. No CHERI support. Holds scalar registers and configuration, all other configuration stored in ProcessorModules32

Fields

running: bool

memory: AggregateMemory

pc: u32

sreg: RvRegisterFile<u32>

csrs: ProcessorCSRs32

Implementations

impl Processor32

pub fn new(mem: AggregateMemory) -> (Processor32, ProcessorModules32)

Create a new processor and vector unit which operates on given memory.

Arguments

• mem - The memory the processor should hold. Currently a value, not a reference.

fn zicsr_conn<'a, 'b>(
    &'a mut self,
    rvv: &'a mut Option<Rv32v>
) -> Zicsr32Conn<'b> where
    'a: 'b, 

fn rv32im_conn<'a, 'b>(&'a mut self) -> Rv32imConn<'b> where
    'a: 'b, 

fn process_inst(
    &mut self,
    mods: &mut ProcessorModules32,
    inst_bits: u32,
    opcode: Opcode,
    inst: InstructionBits
) -> Result<u32>

Process an instruction, returning the new PC value or any execution error

Arguments

• v_unit - The associated vector unit, which will execute vector instructions if they are found.
• inst_bits - The raw instruction bits
• opcode - The major opcode of the decoded instruction
• inst - The fields of the decoded instruction

Trait Implementations

impl Processor<ProcessorModules32> for Processor32

fn reset(&mut self, mods: &mut ProcessorModules32)

Reset the processor and associated vector unit

fn exec_step(&mut self, mods: &mut ProcessorModules32) -> Result<()>

Run a fetch-decode-execute step on the processor, executing a single instruction

Arguments

• v_unit - The associated vector unit, which will execute vector instructions if they are found.

fn dump(&self, mods: &ProcessorModules32)

Dump processor and vector unit state to standard output.

fn running(&self) -> bool

fn get_io_values(&self) -> Vec<Option<u64>>