Module rsim::processor::isa_mods [−][src]
All RISC-V ISA extensions implemented as objects implementing IsaMod.
Re-exports
pub use vector::Rv32v; | |
pub use vector::Rv64v; | |
pub use vector::Rv64Cheriv; |
Modules
| cheri | |
| csrs | |
| rv32im | |
| rv64im | |
| vector |
Structs
| CheriVectorRegisterFile | Register file which holds 128-bit integer vectors OR one tagged capability per vector. |
| IntVectorRegisterFile | Register file which holds 128-bit integer vectors. |
| Rv32im | Base ISA module for RV32 ISAs. Implements Integer and Multiply extensions. |
| Rv64im | Base ISA module for RV64 ISAs. Implements Integer and Multiply extensions. |
| Rv64imCapabilityMode | Override for base RV64I instructions when in “capability mode”. See TR-951$5.3.6, page 152 for list of affected instructions. |
| RvimConn | Connection to a RISC-V I+M ISA module. |
| XCheri64 | ISA module implementing the new CHERI instructions for 64-bit ISAs. Does not include capability-mode overrides for legacy instructions. |
| XCheri64Conn | Connection to register state for 64-bit CHERI-aware ISA modules. Used by XCheri64 and Rv64imCapabilityMode. |
Traits
| CSRProvider | |
| IsaMod | Trait for all ISA modules. |
| PossibleXlen | Trait for possible XLEN values. Used to make elements generic over (u32 or u64). |
Type Definitions
| Rv32imConn | |
| Rv64imConn | |
| Zicsr32 | CSR unit for RV32 ISAs |
| Zicsr32Conn | |
| Zicsr64 | CSR unit for RV64 ISAs |
| Zicsr64Conn |